1. Field of the Invention
The present invention relates to memory cells and especially to memory cells employed in user-programmable integrated circuit devices such as field programmable gate array devices.
2. The Prior Art
Numerous prior memory cells have been proposed for controlling switching in user-programmable integrated circuits. Some prior schemes have employed n-channel nano-crystal or SONOS transistors as pull-down devices and used volatile p-channel transistors as pull-up devices. Other schemes have employed p-channel nano-crystal or SONOS transistors and used volatile re-channel transistors as pull-down devices. Still other schemes have used both re-channel and p-channel nano-crystal or SONOS transistors as pull-down and pull-up devices, respectively, to form push-pull memory cells.
One example of a prior-art device is shown in United states Patent Publication No. 2005/0141266, now abandoned. Another such example is shown in United States Patent Publication No. 2008/0076221.
One of the disadvantages that prior-art solutions are subject to results from the fact that the voltages that are necessary to program and erase the memory devices are significantly higher than the voltages encountered by the devices during normal circuit operation. Because of the presence of these higher voltages during programming and erasing of the memory cells, the other transistor devices associated with the memory cells have to be fabricated to withstand these higher voltages.